This paper presents the hardware verification process of a Singular Value Decomposition (SVD) based OFDM channel estimator. The design has been implemented on a Virtex-II Pro FPGA board and synthesized for an ASIC in 130 nm technology. The design has been verified using the Agilent HP 16822A system consisting of a Logic Analyzer and Pattern Generator. The design has been tested for three different set of random test vectors and worked correctly up to 110 MHz. The verification result shows that successful hardware implementation is possible for this sort of novel, advanced channel estimation strategies, even though no prior implementation and verification of such estimation strategies have been known. Along with the verification process, the paper gives a brief introduction of a SVD based channel estimator and also discusses the hardware synthesis report.